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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>LDP (SIMD&amp;FP) -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">LDP (SIMD&amp;FP)</h2>
      <p class="aml">Load Pair of SIMD&amp;FP registers. This instruction loads a pair of SIMD&amp;FP registers from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset.</p>
      <p class="aml">Depending on the settings in the <a class="armarm-xref" title="Reference to Armv8 ARM section">CPACR_EL1</a>, <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL2</a>, and <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL3</a> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</p>
    
    <p class="desc">
      It has encodings from 3 classes:
      <a href="#iclass_post_indexed">Post-index</a>
      , 
      <a href="#iclass_pre_indexed">Pre-index</a>
       and 
      <a href="#iclass_signed_scaled_offset">Signed offset</a>
    </p>
    <h3 class="classheading"><a id="iclass_post_indexed"/>Post-index</h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td colspan="2" class="lr">opc</td><td class="l">1</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="l">0</td><td>0</td><td class="r">1</td><td class="lr">1</td><td colspan="7" class="lr">imm7</td><td colspan="5" class="lr">Rt2</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="3"/><td/><td colspan="3"/><td class="droppedname">L</td><td colspan="7"/><td colspan="5"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">32-bit<span class="bitdiff"> (opc == 00)</span></h4><a id="LDP_S_ldstpair_post"/><p class="asm-code">LDP  <a href="#sa_st1" title="First 32-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;St1&gt;</a>, <a href="#sa_st2" title="Second 32-bit SIMD&amp;FP register to be transferred (field &quot;Rt2&quot;)">&lt;St2&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>], #<a href="#sa_imm_5" title="Signed immediate byte offset, multiple of 4 [-256-252] (field &quot;imm7&quot;)">&lt;imm&gt;</a></p></div><div class="encoding"><h4 class="encoding">64-bit<span class="bitdiff"> (opc == 01)</span></h4><a id="LDP_D_ldstpair_post"/><p class="asm-code">LDP  <a href="#sa_dt1" title="First 64-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Dt1&gt;</a>, <a href="#sa_dt2" title="Second 64-bit SIMD&amp;FP register to be transferred (field &quot;Rt2&quot;)">&lt;Dt2&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>], #<a href="#sa_imm_1" title="Signed immediate byte offset, multiple of 8 [-512-504] (field &quot;imm7&quot;)">&lt;imm&gt;</a></p></div><div class="encoding"><h4 class="encoding">128-bit<span class="bitdiff"> (opc == 10)</span></h4><a id="LDP_Q_ldstpair_post"/><p class="asm-code">LDP  <a href="#sa_qt1" title="First 128-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Qt1&gt;</a>, <a href="#sa_qt2" title="Second 128-bit SIMD&amp;FP register to be transferred (field &quot;Rt2&quot;)">&lt;Qt2&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>], #<a href="#sa_imm_3" title="Signed immediate byte offset, multiple of 16 [-1024-1008] (field &quot;imm7&quot;)">&lt;imm&gt;</a></p></div><p class="pseudocode">boolean wback = TRUE;
boolean postindex = TRUE;</p>
    <h3 class="classheading"><a id="iclass_pre_indexed"/>Pre-index</h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td colspan="2" class="lr">opc</td><td class="l">1</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="lr">1</td><td colspan="7" class="lr">imm7</td><td colspan="5" class="lr">Rt2</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="3"/><td/><td colspan="3"/><td class="droppedname">L</td><td colspan="7"/><td colspan="5"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">32-bit<span class="bitdiff"> (opc == 00)</span></h4><a id="LDP_S_ldstpair_pre"/><p class="asm-code">LDP  <a href="#sa_st1" title="First 32-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;St1&gt;</a>, <a href="#sa_st2" title="Second 32-bit SIMD&amp;FP register to be transferred (field &quot;Rt2&quot;)">&lt;St2&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>, #<a href="#sa_imm_5" title="Signed immediate byte offset, multiple of 4 [-256-252] (field &quot;imm7&quot;)">&lt;imm&gt;</a>]!</p></div><div class="encoding"><h4 class="encoding">64-bit<span class="bitdiff"> (opc == 01)</span></h4><a id="LDP_D_ldstpair_pre"/><p class="asm-code">LDP  <a href="#sa_dt1" title="First 64-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Dt1&gt;</a>, <a href="#sa_dt2" title="Second 64-bit SIMD&amp;FP register to be transferred (field &quot;Rt2&quot;)">&lt;Dt2&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>, #<a href="#sa_imm_1" title="Signed immediate byte offset, multiple of 8 [-512-504] (field &quot;imm7&quot;)">&lt;imm&gt;</a>]!</p></div><div class="encoding"><h4 class="encoding">128-bit<span class="bitdiff"> (opc == 10)</span></h4><a id="LDP_Q_ldstpair_pre"/><p class="asm-code">LDP  <a href="#sa_qt1" title="First 128-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Qt1&gt;</a>, <a href="#sa_qt2" title="Second 128-bit SIMD&amp;FP register to be transferred (field &quot;Rt2&quot;)">&lt;Qt2&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>, #<a href="#sa_imm_3" title="Signed immediate byte offset, multiple of 16 [-1024-1008] (field &quot;imm7&quot;)">&lt;imm&gt;</a>]!</p></div><p class="pseudocode">boolean wback = TRUE;
boolean postindex = FALSE;</p>
    <h3 class="classheading"><a id="iclass_signed_scaled_offset"/>Signed offset</h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td colspan="2" class="lr">opc</td><td class="l">1</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="l">0</td><td>1</td><td class="r">0</td><td class="lr">1</td><td colspan="7" class="lr">imm7</td><td colspan="5" class="lr">Rt2</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="3"/><td/><td colspan="3"/><td class="droppedname">L</td><td colspan="7"/><td colspan="5"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">32-bit<span class="bitdiff"> (opc == 00)</span></h4><a id="LDP_S_ldstpair_off"/><p class="asm-code">LDP  <a href="#sa_st1" title="First 32-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;St1&gt;</a>, <a href="#sa_st2" title="Second 32-bit SIMD&amp;FP register to be transferred (field &quot;Rt2&quot;)">&lt;St2&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{, #<a href="#sa_imm_4" title="Optional signed immediate byte offset, multiple of 4 [-256-252], default 0 (field &quot;imm7&quot;)">&lt;imm&gt;</a>}]</p></div><div class="encoding"><h4 class="encoding">64-bit<span class="bitdiff"> (opc == 01)</span></h4><a id="LDP_D_ldstpair_off"/><p class="asm-code">LDP  <a href="#sa_dt1" title="First 64-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Dt1&gt;</a>, <a href="#sa_dt2" title="Second 64-bit SIMD&amp;FP register to be transferred (field &quot;Rt2&quot;)">&lt;Dt2&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{, #<a href="#sa_imm" title="Optional signed immediate byte offset, multiple of 8 [-512-504], default 0 (field &quot;imm7&quot;)">&lt;imm&gt;</a>}]</p></div><div class="encoding"><h4 class="encoding">128-bit<span class="bitdiff"> (opc == 10)</span></h4><a id="LDP_Q_ldstpair_off"/><p class="asm-code">LDP  <a href="#sa_qt1" title="First 128-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Qt1&gt;</a>, <a href="#sa_qt2" title="Second 128-bit SIMD&amp;FP register to be transferred (field &quot;Rt2&quot;)">&lt;Qt2&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{, #<a href="#sa_imm_2" title="Optional signed immediate byte offset, multiple of 16 [-1024-1008], default 0 (field &quot;imm7&quot;)">&lt;imm&gt;</a>}]</p></div><p class="pseudocode">boolean wback = FALSE;
boolean postindex = FALSE;</p>
  <div class="encoding-notes">
      <p class="aml">For information about the <span class="arm-defined-word">constrained unpredictable</span> behavior of this instruction, see <a class="armarm-xref" title="Reference to Armv8 ARM section">Architectural Constraints on UNPREDICTABLE behaviors</a>, and particularly <a class="armarm-xref" title="Reference to Armv8 ARM section">LDP (SIMD&amp;FP)</a>.</p>
    </div><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Dt1&gt;</td><td><a id="sa_dt1"/>
        
          <p class="aml">Is the 64-bit name of the first SIMD&amp;FP register to be transferred, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Dt2&gt;</td><td><a id="sa_dt2"/>
        
          <p class="aml">Is the 64-bit name of the second SIMD&amp;FP register to be transferred, encoded in the "Rt2" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Qt1&gt;</td><td><a id="sa_qt1"/>
        
          <p class="aml">Is the 128-bit name of the first SIMD&amp;FP register to be transferred, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Qt2&gt;</td><td><a id="sa_qt2"/>
        
          <p class="aml">Is the 128-bit name of the second SIMD&amp;FP register to be transferred, encoded in the "Rt2" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;St1&gt;</td><td><a id="sa_st1"/>
        
          <p class="aml">Is the 32-bit name of the first SIMD&amp;FP register to be transferred, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;St2&gt;</td><td><a id="sa_st2"/>
        
          <p class="aml">Is the 32-bit name of the second SIMD&amp;FP register to be transferred, encoded in the "Rt2" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xn|SP&gt;</td><td><a id="sa_xn_sp"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;imm&gt;</td><td><a id="sa_imm_5"/>
        
          
          
        
        
          <p class="aml">For the 32-bit post-index and 32-bit pre-index variant: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as &lt;imm&gt;/4.</p>
        
      </td></tr><tr><td/><td><a id="sa_imm_4"/>
        
          
          
          
          
        
        
          <p class="aml">For the 32-bit signed offset variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as &lt;imm&gt;/4.</p>
        
      </td></tr><tr><td/><td><a id="sa_imm_1"/>
        
          
          
        
        
          <p class="aml">For the 64-bit post-index and 64-bit pre-index variant: is the signed immediate byte offset, a multiple of 8 in the range -512 to 504, encoded in the "imm7" field as &lt;imm&gt;/8.</p>
        
      </td></tr><tr><td/><td><a id="sa_imm"/>
        
          
          
          
          
        
        
          <p class="aml">For the 64-bit signed offset variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as &lt;imm&gt;/8.</p>
        
      </td></tr><tr><td/><td><a id="sa_imm_3"/>
        
          
          
        
        
          <p class="aml">For the 128-bit post-index and 128-bit pre-index variant: is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field as &lt;imm&gt;/16.</p>
        
      </td></tr><tr><td/><td><a id="sa_imm_2"/>
        
          
          
          
          
        
        
          <p class="aml">For the 128-bit signed offset variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as &lt;imm&gt;/16.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="postdecode"/><h3 class="pseudocode">Shared Decode</h3>
      <p class="pseudocode">integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer t = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rt);
integer t2 = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rt2);
if opc == '11' then UNDEFINED;
integer scale = 2 + <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(opc);
integer datasize = 8 &lt;&lt; scale;
bits(64) offset = <a href="shared_pseudocode.html#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="shared_pseudocode.html#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm7, 64), scale);
boolean tagchecked = wback || n != 31;

boolean rt_unknown = FALSE;

if t == t2 then
    <a href="shared_pseudocode.html#Constraint" title="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c = <a href="shared_pseudocode.html#impl-shared.ConstrainUnpredictable.1" title="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a href="shared_pseudocode.html#Unpredictable_LDPOVERLAP" title="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,   Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_RESMDSELR,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,   Unpredictable_BPLINKINGDISABLED,  Unpredictable_RESBPMASK,   Unpredictable_BPMASK,  Unpredictable_BPMASKEDBITS,   Unpredictable_BPLINKEDADDRMATCH,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RES_ETBAD,  Unpredictable_RESTC }">Unpredictable_LDPOVERLAP</a>);
    assert c IN {<a href="shared_pseudocode.html#Constraint_UNKNOWN" title="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>, <a href="shared_pseudocode.html#Constraint_UNDEF" title="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a>, <a href="shared_pseudocode.html#Constraint_NOP" title="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a>};
    case c of
        when <a href="shared_pseudocode.html#Constraint_UNKNOWN" title="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a> rt_unknown = TRUE;    // result is UNKNOWN
        when <a href="shared_pseudocode.html#Constraint_UNDEF" title="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a>   UNDEFINED;
        when <a href="shared_pseudocode.html#Constraint_NOP" title="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a>     <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>();</p>
    </div>
  
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckFPEnabled64.0" title="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
bits(64) address;
bits(datasize) data1;
bits(datasize) data2;
constant integer dbytes = datasize DIV 8;

<a href="shared_pseudocode.html#AccessDescriptor" title="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a href="shared_pseudocode.html#impl-shared.CreateAccDescASIMD.3" title="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a href="shared_pseudocode.html#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, FALSE, tagchecked);

if n == 31 then
    <a href="shared_pseudocode.html#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

if !postindex then
    address = address + offset;

data1 = <a href="shared_pseudocode.html#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address, dbytes, accdesc];
data2 = <a href="shared_pseudocode.html#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address+dbytes, dbytes, accdesc];
if rt_unknown then
    data1 = bits(datasize) UNKNOWN;
    data2 = bits(datasize) UNKNOWN;
<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[t, datasize] = data1;
<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[t2, datasize] = data2;

if wback then
    if postindex then
        address = address + offset;
    if n == 31 then
        <a href="shared_pseudocode.html#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(64) value">SP</a>[] = address;
    else
        <a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address;</p>
    </div>
  <h3>Operational information</h3>
    <p class="aml">If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</p>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
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      This document is Non-Confidential.
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